`timescale 1ns / 1ns

module sequence_detect( 
    input clk, 
    input rst_n, 
    input data, 
    output reg match, 
    output reg not_match 
); 

parameter [5:0] list = 6'b010110;
reg [2:0] index; //位选
reg [2:0] right_num;
reg [0:0] is_right;//保存当前6个数字是否正确，正确为1，不正确为0

//控制index
always @(posedge clk or negedge rst_n)begin
    if(!rst_n) begin
        index <= 0;
    end 
    else begin
        if(index == 5)
            index <= 0;
        else 
        index <= index + 1;
    end
end

always @(posedge clk or negedge rst_n)begin
    if(!rst_n) begin
        right_num <=0;
        match <= 0;
    end
    else if(right_num == 5) begin
        right_num <=0;
        match <= 1;
    end 
        else if(is_right)begin
            right_num = right_num + 1;
            match <= 0;
            end
            else begin
                right_num <=0;
                match <= 0;
            end         
end

reg [0:0] not_match_flag;

always @(posedge clk or negedge rst_n)begin
    if(!rst_n) begin
        is_right <= 1;
        not_match <= 0;
        not_match_flag <= 0;
    end 
    else if(index == 5)begin
        is_right <= 1;
        not_match_flag <= 0;
    end  
        else begin
            if(data == list[index] && is_right) //开始判断
                is_right <= 1;
            else begin //匹配错误
                if (not_match==1 && is_right==0 && not_match_flag == 0)begin
                        not_match <= 0;
                        not_match_flag <= 1;
                        is_right <= 0;
                    end
                else begin
                        not_match <= 1;
                        is_right <= 0;
                    end   
            end
        end
end

endmodule 
